Struct raw_cpuid::ExtendedFeatures
source · [−]pub struct ExtendedFeatures { /* private fields */ }Expand description
Implementations
sourceimpl ExtendedFeatures
impl ExtendedFeatures
sourcepub const fn has_fsgsbase(&self) -> bool
pub const fn has_fsgsbase(&self) -> bool
sourcepub const fn has_tsc_adjust_msr(&self) -> bool
pub const fn has_tsc_adjust_msr(&self) -> bool
sourcepub const fn has_fdp(&self) -> bool
pub const fn has_fdp(&self) -> bool
FDP_EXCPTN_ONLY. x87 FPU Data Pointer updated only on x87 exceptions if 1.
Platforms
❌ AMD (reserved) ✅ Intel
sourcepub const fn has_rep_movsb_stosb(&self) -> bool
pub const fn has_rep_movsb_stosb(&self) -> bool
sourcepub const fn has_invpcid(&self) -> bool
pub const fn has_invpcid(&self) -> bool
INVPCID. If 1, supports INVPCID instruction for system software that manages process-context identifiers.
Platforms
❌ AMD (reserved) ✅ Intel
sourcepub const fn has_rdtm(&self) -> bool
pub const fn has_rdtm(&self) -> bool
Supports Intel Resource Director Technology (RDT) Monitoring capability.
Platforms
❌ AMD (reserved) ✅ Intel
sourcepub const fn has_fpu_cs_ds_deprecated(&self) -> bool
pub const fn has_fpu_cs_ds_deprecated(&self) -> bool
sourcepub const fn has_rdta(&self) -> bool
pub const fn has_rdta(&self) -> bool
Supports Intel Resource Director Technology (RDT) Allocation capability.
Platforms
❌ AMD (reserved) ✅ Intel
sourcepub const fn has_rdseed(&self) -> bool
pub const fn has_rdseed(&self) -> bool
sourcepub const fn has_smap(&self) -> bool
pub const fn has_smap(&self) -> bool
SMAP. Supports Supervisor-Mode Access Prevention (and the CLAC/STAC instructions) if 1.
Platforms
✅ AMD ✅ Intel
sourcepub const fn has_clflushopt(&self) -> bool
pub const fn has_clflushopt(&self) -> bool
sourcepub const fn has_processor_trace(&self) -> bool
pub const fn has_processor_trace(&self) -> bool
sourcepub const fn has_sgx(&self) -> bool
pub const fn has_sgx(&self) -> bool
Supports Intel® Software Guard Extensions (Intel® SGX Extensions).
Platforms
❌ AMD (reserved) ✅ Intel
sourcepub const fn has_avx512f(&self) -> bool
pub const fn has_avx512f(&self) -> bool
sourcepub const fn has_avx512dq(&self) -> bool
pub const fn has_avx512dq(&self) -> bool
sourcepub const fn has_avx512_ifma(&self) -> bool
pub const fn has_avx512_ifma(&self) -> bool
sourcepub const fn has_avx512pf(&self) -> bool
pub const fn has_avx512pf(&self) -> bool
sourcepub const fn has_avx512er(&self) -> bool
pub const fn has_avx512er(&self) -> bool
sourcepub const fn has_avx512cd(&self) -> bool
pub const fn has_avx512cd(&self) -> bool
sourcepub const fn has_avx512bw(&self) -> bool
pub const fn has_avx512bw(&self) -> bool
sourcepub const fn has_avx512vl(&self) -> bool
pub const fn has_avx512vl(&self) -> bool
sourcepub const fn has_prefetchwt1(&self) -> bool
pub const fn has_prefetchwt1(&self) -> bool
sourcepub const fn has_ospke(&self) -> bool
pub const fn has_ospke(&self) -> bool
OS has set CR4.PKE to enable protection keys (and the RDPKRU/WRPKRU instructions.
Platforms
❌ AMD (reserved) ✅ Intel
sourcepub const fn has_waitpkg(&self) -> bool
pub const fn has_waitpkg(&self) -> bool
WAITPKG
❓ AMD ✅ Intel
sourcepub const fn has_av512vbmi2(&self) -> bool
pub const fn has_av512vbmi2(&self) -> bool
AVX512VBMI2
❓ AMD ✅ Intel
sourcepub const fn has_cet_ss(&self) -> bool
pub const fn has_cet_ss(&self) -> bool
Supports CET shadow stack features. Processors that set this bit define bits 0..2 of the IA32_U_CET and IA32_S_CET MSRs. Enumerates support for the following MSRs: IA32_INTERRUPT_SPP_TABLE_ADDR, IA32_PL3_SSP, IA32_PL2_SSP, IA32_PL1_SSP, and IA32_PL0_SSP.
❓ AMD ✅ Intel
sourcepub const fn has_vpclmulqdq(&self) -> bool
pub const fn has_vpclmulqdq(&self) -> bool
VPCLMULQDQ
❓ AMD ✅ Intel
sourcepub const fn has_avx512vnni(&self) -> bool
pub const fn has_avx512vnni(&self) -> bool
sourcepub const fn has_avx512bitalg(&self) -> bool
pub const fn has_avx512bitalg(&self) -> bool
AVX512BITALG
❓ AMD ✅ Intel
sourcepub const fn has_tme_en(&self) -> bool
pub const fn has_tme_en(&self) -> bool
Indicates the following MSRs are supported: IA32_TME_CAPABILITY, IA32_TME_ACTIVATE, IA32_TME_EXCLUDE_MASK, and IA32_TME_EXCLUDE_BASE.
❓ AMD ✅ Intel
sourcepub const fn has_avx512vpopcntdq(&self) -> bool
pub const fn has_avx512vpopcntdq(&self) -> bool
AVX512VPOPCNTDQ
❓ AMD ✅ Intel
sourcepub const fn has_sgx_lc(&self) -> bool
pub const fn has_sgx_lc(&self) -> bool
sourcepub fn mawau_value(&self) -> u8
pub fn mawau_value(&self) -> u8
The value of MAWAU used by the BNDLDX and BNDSTX instructions in 64-bit mode.
Platforms
❌ AMD (reserved) ✅ Intel